The following documents are incorporated herein by reference, in their entirety, for their useful technical descriptions related to the background explained below: U.S. patent application publication 20030033580 of Maxwell, et al. dated Feb. 13, 2003; U.S. patent application publication 20060220721 of Nitin, et al. dated Oct. 5, 2006; U.S. patent application publication 20070011643 of Qi; et al. dated Jan. 11, 2007; U.S. patent application publication 20070094623 of Haizhou, et al. dated Apr. 26, 2007; U.S. patent application publication 20070099314 of Haizhou, et al. dated May 3, 2007; U.S. Pat. No. 6,810,482 to Saxena, et al. dated Oct. 26, 2004; U.S. Pat. No. 7,007,247 to Wang, et al dated Feb. 28, 2006; U.S. Pat. No. 7,051,306 to Hoberman, et al. dated May 23, 2006; and U.S. Pat. No. 7,076,748 to Kapoor, et al. dated Jul. 11, 2006.
In recent years, the size of integrated circuits (ICs) has dramatically increased in both size and number of transistors, resulting in higher power consumption. In typical IC designs, the clock distribution network, i.e., the clock tree, can consume from twenty to fifty percent of an IC's total active power. One important technique for reducing power consumption in IC designs is to reduce the power of an IC's clock distribution tree by gating portions of the IC that do not need to be clocked under certain conditions.
This process, known as “clock gating”, disables the clocks fed to logic blocks of the IC when the logic blocks are not currently enabled or otherwise in active use. Power consumption due to the clocking of logic blocks that are not directly involved with the current operation of the IC is thereby minimized.
FIG. 1 shows a partial logic circuit 100 that has not been clock gated. Circuit 100 includes a synchronous load-enable register 110 implementing the load enabling circuit. The clock input port provides the clock signal “CLK” that clocks the register 110 every cycle. The enable port provides an enable signal “EN” that enables the register 110, thereby allowing data propagation from logic 130 to the output of the register 110. Obviously, there is no need to clock the register 110 every cycle, since the data at the input of register 110 does not change every clock cycle.
FIG. 2A shows a partial logic circuit to which a clock gating technique is applied. An integrated clock gating circuit (ICGC) cell 200 is used as the gating circuit. The ICGC 200 includes an AND gate 205 and a flip-flop 210. The clock and the enable ports are connected to an ICGC 200 as its inputs. When the enable signal is set to a logic value ‘1’, data is input to register 110 synchronously with the clock signal “CLK”. On the other hand, when the enable signal is set to a logic value ‘0’, data is not input to register 110 irrespective of the clock signal. Accordingly, when there is no need for loading data to the register 110, unnecessary power consumption can be avoided by outputting the enable signals of a logic zero synchronously with the clock signal.
FIG. 2B shows another technique for clock gating the circuit 100 where a multiplexer (MUX) 220 implements the load enabling. In addition, the output of the register 110 is coupled to one of the inputs of MUX 200. The amount of dynamic power reduction depends upon the technique being implemented, as well as upon several characteristics, such as the enable duty cycle, the bus width and the data activity.
Furthermore, gating all registers in the design increases the size of the IC. As a result, traditional approaches gate all the registers having a size that is greater than a predefined threshold. Alternatively, registers to be clock-gated are manually selected. These approaches are not optimal in terms of power and area cost, as most of the savings can be achieved using only a few clock gating structures.
One solution for selection of the optimal registers to be clock-gated is based on computing the activity savings per each such register. This solution is described in a U.S. patent application Ser. No. 11/419,624 by Kapoor, et al. assigned to common assignee and which is hereby incorporated by reference in its entirety. However, this solution does not compute the power savings for the different clock gating techniques, such as those described above. Furthermore, the computation is limited to clock gates (or “enables”) already existing in the design.
It would be therefore advantageous to provide a more efficient approach for computing the power savings of candidate registers for clock gating implementation.